? semiconductor components industries, llc, 2009 november, 2009 ? rev. 1 1 publication order number: mc74hct132a/d mc74hct132a quad 2-input nand gate with schmitt-trigger inputs with lsttl compatible inputs high ? performance silicon ? gate cmos the mc74hct132a is identical in pinout to the ls132. the device inputs are compatible with standard cmos outputs; with pull ? up resistors, they are compatible with lsttl outputs. the mc74hct132a can be used to enhance noise immunity or to square up slowly changing waveforms. features ? output drive capability: 10 lsttl loads ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 2.0 to 6.0 v ? low input current: 1.0 a ? high noise immunity characteristic of cmos devices ? in compliance with the requirements as defined by jedec standard no. 7a ? chip complexity: 72 fets or 18 equivalent gates ? these are pb ? free devices figure 1. pin assignment 11 12 13 14 8 9 10 5 4 3 2 1 7 6 b3 y4 a4 b4 v cc y3 a3 a2 y1 b1 a1 gnd y2 b2 marking diagrams a = assembly location l, wl = wafer lot y, yy = year w, ww = work week g or = pb ? free package pdip ? 14 n suffix case 646 soic ? 14 d suffix case 751a hct132ag awlyww tssop ? 14 dt suffix case 948g hct 132a alyw 1 14 see detailed ordering and shipping information in the package dimensions section on p age 2 of this data sheet. ordering information inputs output aby llh lhh hlh hhl function table 1 14 http://onsemi.com mc74hct132an awlyywwg 1 14 (note: microdot may be in either location) soeiaj ? 14 f suffix case 965 74hct132a alywg 1 14
mc74hct132a http://onsemi.com 2 figure 2. logic diagram a1 b1 y1 3 2 1 pin 14 = v cc pin 7 = gnd y = ab a2 b2 y2 6 5 4 a3 b3 y3 8 10 9 a4 b4 y4 11 13 12 ordering information device package shipping ? mc74hct132ang pdip ? 14 (pb ? free) 25 / tape & ammo box mc74hct132adg soic ? 14 (pb ? free) 55 units / rail mc74hct132adr2g soic ? 14 (pb ? free) 2500 / tape & reel mc74hct132adtr2g tssop ? 14* 2500 / tape & reel MC74HCT132AFELG soeiaj ? 14 (pb ? free) 2000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *this package is inherently pb ? free.
mc74hct132a http://onsemi.com 3 maximum ratings symbol parameter value unit v cc positive dc supply voltage 0.5 to 7.0 v v in digital input voltage 0.5 to 7.0 v v out dc output voltage output in 3 ? state high or low state 0.5 to 7.0 0.5 to v cc 0.5 v i ik input diode current 20 ma i ok output diode current 20 ma i out dc output current, per pin 25 ma i cc dc supply current, v cc and gnd pins 75 ma i gnd dc ground current per ground pin 75 ma t stg storage temperature range 65 to 150 c t l lead temperature, 1 mm from case for 10 seconds 260 c t j junction temperature under bias 150 c ja thermal resistance 14 ? pdip 14 ? soic 14 ? tssop 78 125 170 c/w p d power dissipation in still air at 85 c pdip soic tssop 750 500 450 mw msl moisture sensitivity level 1 f r flammability rating oxygen index: 30% ? 35% ul 94 v0 @ 0.125 in v esd esd withstand voltage human body model (note 1) machine model (note 2) charged device model (note 3) 2000 100 500 v i latch ? up latch ? up performance above v cc and below gnd at 85 c (note 4) 300 ma stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. tested to eia/jesd22 ? a114 ? a. 2. tested to eia/jesd22 ? a115 ? a. 3. tested to jesd22 ? c101 ? a. 4. tested to eia/jesd78. recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 2.0 6.0 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types 55 125 c t r , t f input rise and fall time (figure 3) ? no limit (note 5) ns 5. when v in 0.5 v cc , i cc >> quiescent current. 6. unused inputs may not be left open. all inputs must be tied to a high ? logic voltage level or a low ? logic input voltage level.
mc74hct132a http://onsemi.com 4 dc electrical characteristics (voltages referenced to gnd) v cc guaranteed limit symbol parameter test conditions v 55 c to 25 c 85 c 125 c unit v t+ max maximum positive ? going input threshold voltage v out = 0.1 v |i out | 20 a 4.5 5.5 1.9 2.1 1.9 2.1 1.9 2.1 v v t+ min minimum positive ? going input threshold voltage v out = 0.1 v |i out | 20 a 4.5 5.5 1.2 1.4 1.2 1.4 1.2 1.4 v v t? max maximum negative ? going input threshold voltage v out = v cc ? 0.1 v |i out | 20 a 4.5 5.5 1.2 1.4 1.2 1.4 1.2 1.4 v v t? min minimum negative ? going input threshold voltage v out = v cc ? 0.1 v |i out | 20 a 4.5 5.5 0.5 0.6 0.5 0.6 0.5 0.6 v v h min (note 7) minimum hysteresis voltage v out = 0.1 v or v cc ? 0.1 v |i out | 20 a 4.5 5.5 0.4 0.4 0.4 0.4 0.4 0.4 v v oh minimum high ? level output voltage v in v t ? min or v t+ max |i out | 20 a 4.5 5.5 4.4 5.4 4.4 5.4 4.4 5.4 v v in ? v t ? min or v t+ max |i out | 4.0 ma 4.5 3.98 3.84 3.7 v ol maximum low ? level output voltage v in v t+ max |i out | 20 a 4.5 5.5 0.1 0.1 0.1 0.1 0.1 0.1 v v in v t+ max |i out | 4.0 ma 4.5 0.26 0.33 0.4 i in maximum input leakage current v in = v cc or gnd 5.5 0.1 1.0 1.0 a i cc maximum quiescent supply current (per package) v in = v cc or gnd i out = 0 a 5.5 1.0 10 40 a 7. v h min (v t+ min) (v t ? max); v h max = (v t+ max) (v t ? min). ac electrical characteristics (c l = 50 pf, input t r = t f = 6.0 ns, v cc = 5.0 v 10%) v cc guaranteed limit symbol parameter v 55 c to 25 c 85 c 125 c unit t plh , t phl maximum propagation delay, input a or b to output y (figures 3 and 4) 5.0 25 31 38 ns t tlh , t thl maximum output transition time, any output (figures 3 and 4) 5.0 15 19 22 ns c in maximum input capacitance ? 10 10 10 pf typical @ 25 c, v cc = 5.0 v c pd power dissipation capacitance (per gate) (note 8) 24 pf 8. used to determine the no ? load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc .
mc74hct132a http://onsemi.com 5 figure 3. switching waveforms t r v cc gnd 90% v m 10% 90% v m 10% input a or b ( v i ) y t phl t plh t thl t tlh *includes all probe and jig capacitance figure 4. test circuit c l * test point device under test output t f v i = gnd to 3.0 v v m = 1.3 v figure 5. typical schmitt ? trigger applications (a)a schmitt trigger squares up inputs (a) with slow rise and fall times (b)a schmitt trigger offers maximum noise immunity v in v out v h v cc v t+ v t- gnd v oh v ol v in v h v out v cc v t+ v t- gnd v oh v ol v cc v in v out
mc74hct132a http://onsemi.com 6 package dimensions pdip ? 14 case 646 ? 06 issue p 17 14 8 b a dim min max min max millimeters inches a 0.715 0.770 18.16 19.56 b 0.240 0.260 6.10 6.60 c 0.145 0.185 3.69 4.69 d 0.015 0.021 0.38 0.53 f 0.040 0.070 1.02 1.78 g 0.100 bsc 2.54 bsc h 0.052 0.095 1.32 2.41 j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l m ??? 10 ??? 10 n 0.015 0.039 0.38 1.01 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. f hg d k c seating plane n ? t ? 14 pl m 0.13 (0.005) l m j 0.290 0.310 7.37 7.87
mc74hct132a http://onsemi.com 7 package dimensions soic ? 14 case 751a ? 03 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. ? a ? ? b ? g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t ? t ? f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019 7.04 14x 0.58 14x 1.52 1.27 dimensions: millimeters 1 pitch soldering footprint* 7x *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mc74hct132a http://onsemi.com 8 package dimensions tssop ? 14 case 948g ? 01 issue b dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.50 0.60 0.020 0.024 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . s u 0.15 (0.006) t 2x l/2 s u m 0.10 (0.004) v s t l ? u ? seating plane 0.10 (0.004) ? t ? ??? ??? section n ? n detail e j j1 k k1 ? w ? 0.25 (0.010) 8 14 7 1 pin 1 ident. h g a d c b s u 0.15 (0.006) t ? v ? 14x ref k n n 7.06 14x 0.36 14x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mc74hct132a http://onsemi.com 9 package dimensions soeiaj ? 14 case 965 ? 01 issue b h e a 1 l e q 1 0.13 (0.005) m 0.10 (0.004) d z e 1 14 8 7 e a b view p c l detail p m dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.10 0.20 0.004 0.008 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 1.42 --- 0.056 a 1 h e q 1 l e 10 0 10 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). a b c d e e l m z on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 mc74hct132a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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